Using FPGA for video processing in video surveillance systems
Video surveillance systems are an important component of train stations, airports, banks, entertainment venues, shopping centers and even home security. As security risks increase, the need for visual monitoring and logging of events has proliferated in multiple usage patterns. As a result, the new architecture must provide scalability for cost-effective solutions across a full range of increasingly complex video surveillance systems. This article refers to the address: http://
Time-to-market pressures, new CODEC standards, and increasingly broad requirements (including advanced target detection, motion detection, target tracking, and target tracking features) are just a few of the challenges facing the new video surveillance architecture. Along with the challenge is the need to scale to implementations with different performance ranges.
Video surveillance and DVR system
Digital video recorders (DVRs) in digital surveillance systems are rapidly adopting advanced digital video compression. Most DVR manufacturers are moving from MPEG-4 to H.264 high definition (HD) CODECs, and the need for higher resolution and compression speeds has increased. Application-Specific Chips (ASSP) are useful for high-volume applications, but lack flexibility, high development costs, and long development times; most advanced digital media processors can only perform H.264 HD decoding (and H.264 HD encoding) More complicated than decoding). The best solution for meeting H.264 HD performance requirements is to use an FPGA plus an external DSP or digital media processor.
Motion detection, video scaling, color space conversion, hard disk interface and DDR2 memory interface can be further extended with low-cost Xilinx FPGAs, and two 27MHz ITU-R BT656 data streams can be time-multiplexed into a single 54MHz data stream. At the same time, it provides video acceleration for the DSP processor. To multiplex two ITU-R BT656 data streams into one ITU-R BT656 data stream, only one channel video port is required to independently transmit the complete two-channel video data. This is a very useful way to provide an interface to a digital media processor with only one ITU-R BT656 video input port. Figure 1 shows a block diagram of such a proposed architecture.
For DVR designs using Texas Instruments' DaVinci processor (only one ITU-R BT656 video input port), a more efficient implementation is needed to time-multiplex multiplex two or more ITU-R BT656 data streams into one The VLYNQ data stream can then be delivered to the DaVinci processor. With the above implementation, video streams can be transported with much fewer I/O pins and system cost can be reduced because the package of the device can be made smaller. Figure 2 shows a block diagram of this design.
PC expansion card DVR system
The PCI bus has provided a good service for PCs over the past decade. However, the bandwidth required by today's PC expansion card DVR systems has far exceeded the capabilities of the PCI bus. Uncompressed video data (after stripping blank frames) is approximately 165 Mbps. Therefore, with an overall PCI bandwidth of 1 Gbps, a maximum of 6 uncompressed video capture or video playback devices can be mixed on a single PCI bus. If the MPEG-4 CODEC chipset is used on an expansion card to reduce the bandwidth on the bus, this will increase the cost and will be limited by the existing MPEG-4 chipset.
PCI Express (PCIe) technology dramatically increases traffic. PCI Express is broken down into multiple channels. Each channel contains one differential pair in each direction, and each differential pair has a data flow of 2 Gbps. Each PCIe slot on the motherboard has its own channel that is not shared with any other slot. Each slot is configured for 16 channels (also known as x16), 8 channels (x8), 4 channels (x4), or 1 channel (x1). PCIe allows the amount of data per card to range from 2 Gbps for x1 channels to 32 Gbps for x16 channels. With PCIe data traffic, you can get rid of the limitations of 6 uncompressed video channels per PCI card.
Using the same design as shown in Figure 1, the PC expansion card DVR system can be implemented quickly and easily by replacing the digital media processor with a PC and caching the video stream to the PC via the PCIe bus. The video analog-to-digital converter produces four separate digital ITU-R BT656 streams that are then sent to a low-cost Spartan-3 device for pre-processing. In the FPGA, the video data is stripped of the blank frames and synchronized, packaged appropriately for PCIe, and fed into the Xilinx PCIe core. The software can then read and play the incoming video, process it, or save it to disk. Figure 3 shows the design of a PC expansion card video surveillance system.
Xilinx video and image processing algorithms
From polyphase video converters, 2D FIR filters and screen displays to simple effects such as overlay and alpha blending, to format and color space conversion, Xilinx FPGAs are ideal for real-time digital video, image processing and filtering. Table 1 lists the application guides for some common video IP block groups.
The DSP processing power of Xilinx FPGAs supports very high resolution (up to 1080p) and reduces the size of large DSP arrays.
Xilinx provides a suite of video IP blocks for rapid design, simulation, implementation and verification of video and image processing algorithms in video surveillance systems. This includes basic primitives and advanced algorithms for designing DVRs.
In addition, Xilinx and its partners offer a range of compression encoding, decoding and codec solutions, from off-the-shelf cores for those who need fast implementations, to the desire to differentiate their products with high quality and low bitrate. Different people provide construction module reference designs and hardware platforms.
Using Xilinx FPGAs for extremely heavy processing tasks in some codec modules, it can support multi-channel HD encoding, saving valuable system processor cycles, reducing or eliminating the cost savings of DSP processor arrays, and easily More functionality and capabilities of the interface to further video processing are integrated into the system. Most importantly, FPGAs provide a scalable solution to support different configurations, additional channels, or new codecs in the same system.
Xilinx FPGAs further reduce DVR system costs by enhancing system logic and implementing new peripherals. Xilinx and its partners also provide system interfaces for the rapid development of video surveillance systems: advanced memory interfaces, PCI Express, Texas Instruments VLYNQ and EMIF interfaces, hard disk interfaces, and ITU-R BT656 interfaces.
Xilinx tools simplify design
Xilinx System Generator for DSP allows you to build and debug high-performance DVR systems in Simulink using the Xilinx Video IP Blockset. Develop and implement video processing algorithms with System Generator for designs that are thoroughly validated and easily implemented.
Xilinx has developed a variety of pre-tested new video IP module sets. Save time by writing these basic building blocks in HDL by easily building video/imaging systems by dragging and dropping modules within System Generator.
In order to handle the huge video data stream from the development board to the PC, System Generator for DSP introduces another novel high-speed hardware co-simulation (via Ethernet interface). This interface allows for low latency, high traffic and has proven to be extremely useful for building video/imaging systems in the System Generator environment.
Another design tool based on the MATLAB language is the AccelDSP synthesis tool developed by Xilinx, a tool based on the advanced MATLAB language for designing DSP blocks for Xilinx FPGAs. This tool enables automatic conversion from floating point to fixed point, generates a synthesizable VHDL or Verilog language, and creates a testbench for verification. You can also use the MATLAB algorithm to generate a fixed-point C++ model or a System Generator module. AccelDSP is a key component of the Xilinx XtremeDSP solution, which combines state-of-the-art FPGAs, design tools, intellectual property cores, partnerships, and design and education services.
In video surveillance systems, video signals are generated by multiple cameras. The FPGA receives the digital video in the ITU-R BT656 format from the video decoder, and then outputs the processed video to the monitor for display, and outputs it to the digital media processor or DSP for compression and storage to the hard disk.
With Xilinx FPGAs, standards-compliant systems can be differentiated from competitors' products while providing the best balance for your application. With Xilinx's portfolio of video IP blocks, it's easy to build a highly flexible and scalable DVR system that meets both the low-end and high-end markets. By integrating the PCIe core with the video IP block group, a low-cost PC expansion card video surveillance system can be developed. Using the VLYNQ core in Xilinx FPGAs, many video streams from multiple cameras can be easily connected to TI's DaVinci processors via Xilinx FPGAs.
The integration of AccelChip with Xilinx System Generator combines the MATLAB-based algorithm synthesis that algorithm developers favor with the graphical design flow used by system engineers and hardware designers. It uses the rich MATLAB language and its accompanying toolbox to create System Generator IP blocks for complex DSP algorithms. By combining these tools, the design team can take advantage of the most efficient means of hardware modeling for implementation, allowing algorithm developers to fully participate in the FPGA design process and achieve better designs faster.
Video surveillance systems are an important component of train stations, airports, banks, entertainment venues, shopping centers and even home security. As security risks increase, the need for visual monitoring and logging of events has proliferated in multiple usage patterns. As a result, the new architecture must provide scalability for cost-effective solutions across a full range of increasingly complex video surveillance systems.
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