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    Who is the "boss" of the audio clock, who is the Lord, and who is from?

    Traditional I2S - Why include the system clock?
    In the past, we occasionally mentioned I2S when discussing audio topics. I mentioned I2S in some of the previous articles, and others will mention it when doing audio research. In short, it is a synchronization method that transfers stereo data from one end to the other.

    This article refers to the address: http://

    Most people think that I2S has three kinds of signals:
    1. Data: input or output data
    2. Bit clock (BCK): A signal that establishes the boundary between two adjacent bits in a data stream.
    3. Left/Right Clock (LRCK)/Wordclock (Wordclock): A slow clock that operates at a sample rate with a 50% duty cycle that establishes between two adjacent channels (left and right) in the data stream. The border.

    The behind-the-scenes hero of I2S is the master clock (MCK), also known as the system clock (SCK), which is often ignored by digital signal processor (DSP) programmers and other processor enthusiasts. The master clock (MCK/SCK) is typically a clock of 64, 128, 256, and 512 times the sample rate (FS). It can be supplied directly from an input pin or internally by some phase-locked loop (PLL).

    In general, DSPs do not require an audio master clock because they can process the data at a completely different rate and then drive the data into the output buffer at some rate (or through the input buffer) driven by BCK and LRCK. Receive data).


    If you can temporarily remove your attention from your processor, you will find that the audio master clock is much more important. Most of the MCK/SCK input audio converters require clock synchronization, while others allow for out of phase. This means that they need to be provided by the same high-speed clock and then removed. Some of the customers I've worked with will tell me in a sudden inspiration: "My ADC needs an MCK, but it's too far away from my DAC. So I have to place a crystal next to each converter..." The idea can be understood, but please "Don't do this!"

    When you purchase a crystal, you cannot guarantee that it is exactly 48.000 kHz. Your analog-to-digital converter (ADC) crystal may operate with an accuracy of +5%, while a digital-to-analog converter (DAC) may operate with an accuracy of a€“5%. This precision will have catastrophic consequences for your design! Why is this? The following will tell you.

    For I2S

    Master clock for audio ADC

    As shown in Figure 1, a high-speed master clock (for example, a 24.576 MHz clock) is used to drive the ADC's oversampling modulator. The data from the oversampling modulator is then decomposed into the sample rate given by LRCK.

    When the ADC is operating in Master mode (generating BCK and LRCK as outputs), the ADC simply divides the MCK/SCK to generate the LRCK and BCK signals. That's right! LRCK/BCK and the master clock are synchronized - the phase may also be synchronized (unless it is a special splitter).

    1.jpg

    Figure 1 General ADC structure diagram

    If acting as a slave and the master clock is out of sync, it will produce too much or too little data so that the digital decker cannot fit just the output word. Under these conditions, many ADCs refuse to stream data.

    The same is true for DAC. Figure 2 shows an advanced DAC block diagram. Here, the interpolator needs to be run through MCK/SCK, and the MCK/SCK also drives the ?”a?‘ modulator. If MCK/SCK is not an integral multiple of the sample rate (64/128/256/512), erroneous data may appear at the ?”a?‘ modulator output.

    1.jpg

    Figure 2 General DAC structure diagram

    Where am I/how do I generate MCK/SCK?
    In today's industrial applications, CMOS oscillators are supported by many crystal oscillators and are in close proximity to these crystal oscillators. They all have very good precision and low jitter. Voltage controlled oscillators (VCOs) are occasionally used, but they are plagued by their output jitter.

    Many modern audio converters now integrate a PLL to generate the MCK through slow BCK. This is very effective. However, you should be aware that there is always the possibility of jitter when using the PLL, which reduces audio performance.

    In addition, I recommend that if you choose between the crystal source driving the ADC or the DAC, please choose to run the ADC through a crystal generation source. If the input is terrible, then what you do will not help! (Like you can't polish the mud!)

    Therefore, the principle that my proposal follows is:
    1. If the converter is an I2S slave, you must supply all three I2S clocks (MCK, BCK, and LRCK) through the same source (or the internal PLL if the converter is included).
    2. If the converter is an I2S master, be sure to provide a reliable, jitter-free MCK source. Then let the converter allocate itself. When possible, let the ADC operate in master mode with a reliable low-jitter MCK source. This ensures the lowest jitter and minimum high frequency distortion.

    Suggested information:
    a€¢ "About dithering" by: Dan Lavry, Lavry Engineering Company, Copyright ?? 1997.

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